The present invention relates to a high quality silicon wafer used as a substrate of semiconductor devices such as memories, a single crystal for producing the same and a method for producing a single crystal.
An example of silicon single crystal pulling apparatus based on the Czochralski method (CZ method) is shown in FIG. 6. This silicon single crystal pulling apparatus comprises a quartz crucible 5 filled with silicon melt 4, a graphite crucible 6 that protects the quartz crucible 5, a heater 7 that is disposed so as to surround the crucibles 5 and 6, and a heat insulating material 8, which are disposed in a main chamber 1, and a pulling chamber 2 for accommodating and taking out a grown single crystal 3 is continuously provided on the main chamber 1 To grow the single crystal 3 by using such a production apparatus, a seed crystal is immersed into the silicon melt 4 in the quartz crucible 5, and then, after necking, carefully pulled with rotation to grow the rod-like single crystal 3. The crucibles 5 and 6 can be moved upwardly or downwardly along the crystal growth axis, and the crucibles are elevated so as to compensate the depression of liquid surface of the melt decreased due to crystallization during the crystal growth, thereby maintaining the height of the melt surface to be constant. Further, into the main chamber 1, an inert gas such as argon gas is introduced from a gas inlet 10 provided at an upper part of the pulling chamber 2, passed through a space between the single crystal 3 under pulling and a gas flow guide cylinder 11 and a space between a lower portion of a heat shielding member 12 and the melt surface, and then discharged from a gas outlet 9.
A large amount of silicon single crystals produced by the aforementioned CZ method are used for semiconductor devices. On the other hand, with use of higher integration degree of semiconductor devices, the devices increasingly become finer, and a size of 0.13 to 0.18 xcexcm is used as a design rule in the latest devices. The use of such finer devices as described above makes the demand for quality of silicon single crystals severer, and the size of crystal defects causing problems also become smaller. If the defect size is smaller than the design rule, a defect will not exist over a plurality of devices, and therefore a device isolation can be surely performed. Moreover, since smaller defects are more likely to be eliminated during the device production process, and therefore less adversely affect on the devices. The size of crystal defect observed as COP (Crystal Originated Particle, defect originated in crystal and observed as a particle after SC1 cleaning) causing problems is currently considered 0.12 xcexcm or more. Therefore, it has become important to reduce defects having a size of 0.1 xcexcm or more as much as possible.
For the reference of the explanation of those defects, there will be given first general knowledge of factors determining densities of defects introduced into silicon single crystals, a void type point defect called vacancy (occasionally abbreviated as V hereinafter), and an interstitial type silicon point defect called interstitial silicon (occasionally abbreviated as I hereinafter).
In a silicon single crystal, a V-region means a region of which F/G is larger than that of a region suffering from the generation of OSFs and which contains many vacancies, i.e., depressions, pits and so forth generated due to lack of silicon atoms, and an I-region means a region containing many dislocations and aggregations of excessive silicon atoms generated due to the presence of excessive amount of silicon atoms. Between the V-region and the I-region, there should be a neutral region (occasionally abbreviated as N-region hereinafter) with no (or little) shortage or no (or little) surplus of the atoms. It has become clear that grown-in defects (FPD, LSTD, COP etc.) should be generated strictly only with supersaturated V or I, and they would not be present as defects even though there is little unevenness of atoms so long as V or I is not saturated.
It is known that the densities of these two kinds of point defects are determined by the relationship between the crystal pulling rate (growing rate) and the temperature gradient G in the vicinity of the solid-liquid interface in the crystal in the CZ method. Further, it has been confirmed that defects distributed in a ring shape called OSF (Oxidation Induced Stacking Fault) are present in the N-region between the V-region and the I-region.
Those defects generated during the crystal growth are categorized as follows. For example, when the growth rate is relatively high, i.e., around 0.6 mm/min or higher, grown-in defects considered to be originated from voids, i.e., aggregations of void-type point defects, such as FPD, LSTD and COP are distributed over the entire plane of the crystal along the radial direction at a high density and degrade the oxide film characteristics. A region containing such defects is called V-rich region. When the growth rate is 0.6 mm/min or lower, Interstitial becomes dominant and the aforementioned OSF ring is initially generated at the circumferential part of the crystal with the decrease of the growth rate, and L/D (large dislocations, also called interstitial dislocation loop, which includes LSEPD, LFPD and so forth), which are considered to be originated from dislocation loops, are present outside the ring at a low density and cause serious failure such as leakage. A region containing such defects is called I-rich region. When the growth rate is further lowered to around 0.4 mm/min, the OSF ring shrinks toward the center of wafer and disappears, and thus the entire plane becomes the I-rich region.
As a method for producing a single crystal that can provide good defect characteristics, there is, for example, a technique disclosed in Japanese Patent Laid-open (Kokai) Publication No. 8-330316, in which incorporation of point defects is controlled. While a crystal is generally grown with growth conditions that make the V-rich region dominant, it is grown in the N-region that is an intermediate region in which the either kind of the point defects is not dominant in the disclosed technique mentioned above. It is said that a crystal free from COPs and so forth can be produced according to this method.
However, the crystal growth rate becomes 0.5 mm/min or less, which is markedly lower than a rate of about 1 mm/min used for usual crystals. Thus, the productivity is degraded and the cost will become higher. Further, the N-region suffers from a drawback that it is likely to cause non-uniform oxygen precipitation.
Meanwhile, Japanese Patent Laid-open Publication No. 11-116391 discloses a method that does not elicit the incorporated void-type point defects by preventing them from growing to a large size. In this technique, it is attempted to decrease COP defects by shortening the period of passing a temperature region of 1150xc2x0 C. to 1080xc2x0 C., in which the point defects considered to agglomerate and grow into COPs. However, it is not considered that the defects are sufficiently reduced by this disclosed technique, since there remain about 10 count/cm2 or less of particles having a size of 0.10 xcexcm or more.
In view of the aforementioned problems of the conventional techniques, an object of the present invention is to provide a production technique that can improve productivity and reduce cost for high quality silicon wafers of excellent device characteristics that sufficiently meet recent devices having a line width of 0.13 to 0.18 xcexcm by further reducing density and size of defects such as COP.
In order to achieve the aforementioned object, the silicon wafer according to the present invention is a mirror surface silicon wafer sliced from a silicon single crystal ingot grown by the Czochralski method under such conditions that V-rich region should become dominant, wherein a count number of particles having a size of 0.1 xcexcm or more is 1 count/cm2 or less when particles are counted by using a particle counter.
The mirror surface silicon wafer sliced from a silicon single crystal ingot grown by the Czochralski method under such conditions that V-rich region should become dominant and having a count number of 1 count/cm2 or less for particles having a size of 0.1 xcexcm or more according to the present invention as described above has very small defects and a low defect density. Therefore, besides it is a high quality silicon wafer showing excellent device characteristics that can satisfactorily meet to recent devices, it can be obtained with a low cost, since it is grown at a high rate in V-rich region.
In this case, the count number of particles having a size of 0.1 xcexcm or more is preferably 0.1 count/cm2 or less.
According to the present invention, there can be provided a wafer having an extremely low defect density, i.e., a count number of 0.1 count/cm2 or less for particles having a size of 0.1 xcexcm or more, as described above.
The method for producing a silicon single crystal according to the present invention is a method wherein, when a silicon single crystal is grown by the Czochralski method, the crystal is grown with a time L/F (min) of 0.28/(F/Gxe2x88x920.225)2 min or less for passing a temperature region of from 1150xc2x0 C. to 1080xc2x0 C. and F/G of 0.22 mm2/Kxc2x7min or more, which are calculated from a temperature gradient G (K/mm) at a crystal center along a crystal pulling axis direction from the melting point of silicon to 1400xc2x0 C., a length L (mm) of the temperature region of from 1150xc2x0 C. to 1080xc2x0 C. and a crystal growth rate F (mm/min)
If a crystal is grown with a defined F/G value and passage time for the temperature region of 1150xc2x0 C. to 1080xc2x0 C. as described above, the total amount of introduced vacancies that form COP defects can be made few, and COP defect size can be limited to a small size by shortening the passage time. Thus, the good yields for device characteristics and oxide dielectric breakdown voltage characteristics are also improved and a silicon single crystal and wafer having an extremely low defect density for the whole plane can be stably produced while maintaining a high productivity.
In this case, a crystal is desirably grown with a time L/F of 40 min or less for passing the temperature region of from 1150xc2x0 C. to 1080xc2x0 C. and F/G of 0.27 mm2/Kxc2x7min or less.
With such conditions, more stable extremely low defect density can be achieved.
Further, in the production of a silicon single crystal according to the present invention, it can be doped with nitrogen.
By doping with nitrogen as described above, the COP size can be further reduced compared with a case without doping.
In this case, nitrogen concentration to be doped is preferably 1xc3x971015 number/cm3 or less.
This is because, in such a nitrogen concentration range, OSFs are not generated and COP defect size can further be effectively reduced by the intentional nitrogen doping.
According to the present invention, there are further provided a silicon single crystal grown by the aforementioned production method in which density and size of defects such as COPs are further reduced, and a high quality silicon wafer sliced from the aforementioned silicon single crystal.
As explained above in detail, according to the crystal growth conditions of the present invention, both of density and size of defects such as COPs in a silicon crystal can be decreased, and there can be provided a high quality silicon wafer having extremely few defects, which does not adversely affect device characteristics, oxide dielectric breakdown voltage characteristics and so forth. Furthermore, a crystal that does not generate defects of a size that poses a problem on the device production can be produced at a crystal growth rate comparable to or faster than that conventionally used, and thus improvement of productivity and cost reduction can be attained.